With regard to flash memories up to the 0.13 μm generation, in order to miniaturize a flash memory, a dominant way of making smaller a flash memory is to make smaller a cell area using a Floating Gate (FG) type or to make thinner an insulating film. However, from the 90 nm generation on, it becomes difficult to make thinner the insulating film in view of securing retention characteristics, and hence a trap type memory which uses as a charge storage layer a trap in an insulating film is attracting attention.
A Twin MONOS (Metal Oxide Nitride Oxide Semiconductor) type storage device is one type of trap type nonvolatile memories (see Japanese Patent Application Laid-Open No. 2005-142600 (Patent Document 1), for example).
FIG. 1 is a plan view of a Twin MONOS type storage device.
As illustrated in FIG. 1, in a Twin MONOS type storage device, a device isolation region 7 is disposed in predetermined regions in a semiconductor substrate to define active regions including source-drain regions 5 and 6. The active regions are crossed by a plurality of word gate electrodes 1. Control gates 21 and 22 (CG1 and CG2) are formed on both sides of the word gate electrode 1 with a trap insulating film 4 sandwiched therebetween. The trap insulating film 4 includes a charge trap layer and is extended between the control gates 21 and 22 and the substrate. A word gate insulating film 3 which does not include a charge trap layer is formed between the gate electrode 1 and the active region.
FIG. 2A and FIG. 2B are sectional views taken along the lines I-I′ and II-II′, respectively, of FIG. 1.
As illustrated in FIG. 2A and FIG. 2B, there are provided three gate electrodes adjacent to one another and source-drain regions on a silicon substrate 8. The trap insulating film 4 is formed between the control gates 21 and 22 and the silicon substrate 8 and between the control gates 21 and 22 and the word gate electrode 1. The word gate insulating film 3 not including a trap is formed below the word gate electrode 1.
By injecting and storing charge into the trap insulating film 4 below the control gate 21 or the control gate 22 using channel hot electrons, the Twin MONOS type storage device operates as a nonvolatile memory which stores 2 bits per cell. When the state of charge below the control gate 22 is read, the left source-drain region 6 is used as a drain to which a positive voltage is applied. At the same time, a positive voltage is also applied to the control gates 21 and 22 and to the word gate electrode 1. When electrons are stored in the trap insulating film 4 below the control gate 22, the flat band of the control gate 22 fluctuates in a positive direction, and hence it becomes difficult for electrons to pass below the control gate 22. On the other hand, when electrons are not stored in the trap insulating film below the control gate 22, a larger amount of current passes. In order to increase the operation speed of the memory, it is necessary that the read current when the charge is erased be high, but, when the Twin MONOS type structure is used, there is a problem that the read current becomes low.
FIG. 3 illustrates an electronic current le when the state of charge stored below the control gate 22 is read and the potential φ felt by the electrons. Further, electric fields applied from the word gate electrode and the control gates are illustrated by arrows. In this case, for example, 2 V is applied to the word gate electrode 1 and the control gates 21 and 22, 1 V is applied to the source-drain region 6, and ground potential is applied to the source-drain region 5 to carry out reading.
As illustrated in FIG. 3, a gap G which corresponds to the thickness of the trap insulating film exists between the word gate electrode and the control gates, and the electric fields from the word gate electrode and the control gates are difficult to be reached to a channel region corresponding to the gap. Specifically, a potential barrier is generated in the vicinity of the gap between the word gate electrode and the control gates, which makes smaller the electronic current Ie.
On the other hand, a cell structure in which the thickness of an insulating film between a word gate electrode and control gates is set independently of an insulating film below the control gates is proposed (see, for example, Japanese Patent Application Laid-Open No. 2001-230332 (Patent Document 2) and Japanese Patent Application Laid-Open No. 2004-282029 (Patent Document 3)).
In the cell structure, as illustrated in FIG. 4, an insulating film 13 which does not have a charge trap is interposed between the word gate electrode 1 and the control gates 21 and 22. In this case, by making thin the insulating film 13, the potential barrier is reduced to increase on-current. However, by making thin the insulating film between the word gate electrode and the control gates, a capacitance C between the word gate electrode and the control gates is increased, which lowers the switching speed of the control gates and the word gate.